Our Lab is a part of the Informatics Faculty at the University of Lugano. The Lab was established in 2006 when Prof. Sharygina received a career award from the Tasso Foundation. The Lab projects focus on automated formal verification with a particular interest in software/hardware model checking, information security, static analysis, abstract interpretation, and decision procedures. We create both theoretical frameworks and practical tools to enable sound and scalable verification of industrial-size systems. For questions about the Lab projects contact natasha.sharygina@usi.ch. We have NEW open PhD and Postdoc positions. For more information, contact natasha.sharygina@usi.ch. |
Formal Verification and Security Lab
Our Lab is a part of the Informatics Faculty at the University of Lugano. The Lab was established in 2006 when Prof. Sharygina received a career award from the Tasso Foundation. The Lab projects focus on automated formal verification with a particular interest in software/hardware model checking, information security, static analysis, abstract interpretation, and decision procedures. We create both theoretical frameworks and practical tools to enable sound and scalable verification of industrial-size systems. For questions about the Lab projects contact natasha.sharygina@usi.ch. We have NEW open PhD and Postdoc positions. For more information, contact natasha.sharygina@usi.ch. |
Latest news
2020-10-24 |
Matteo Marescotti defended his PhD thesis "Parallelization and modeling techniques for scalable SMT-based verification" (05.10.2020) |
2020-09-21 |
Our paper on Farkas-Based Tree Interpolation has been accepted to SAS 2020 |
2020-07-17 |
Our paper on Incremental Verification by SMT-based Summary Repair has been accepted to FMCAD 2020 |
2020-07-10 |
Our SMT-solver OpenSMT won the QF_LRA Single Query Track of the SMT competition 2020 |
2020-07-10 |
Our paper Accurate Smart Contract Verification through Direct Modelling has been accepted to ISoLA 2020 |