Our Lab is a part of the Informatics Faculty at the University of Lugano. The Lab was established in 2006 when Prof. Sharygina received a career award from the Tasso Foundation. The Lab projects focus on automated formal verification with a particular interest in software/hardware model checking, information security, static analysis, abstract interpretation, and decision procedures. We create both theoretical frameworks and practical tools to enable sound and scalable verification of industrial-size systems. For questions about the Lab projects contact natasha.sharygina@usi.ch. We have NEW open PhD and Postdoc positions. For more information, contact natasha.sharygina@usi.ch. |
Formal Verification and Security Lab
Our Lab is a part of the Informatics Faculty at the University of Lugano. The Lab was established in 2006 when Prof. Sharygina received a career award from the Tasso Foundation. The Lab projects focus on automated formal verification with a particular interest in software/hardware model checking, information security, static analysis, abstract interpretation, and decision procedures. We create both theoretical frameworks and practical tools to enable sound and scalable verification of industrial-size systems. For questions about the Lab projects contact natasha.sharygina@usi.ch. We have NEW open PhD and Postdoc positions. For more information, contact natasha.sharygina@usi.ch. |
Latest news
2021-10-23 |
Our paper Lookahead in Partitioning SMT has been accepted to Formal Methods in Computer-Aided Design - FMCAD 2021 |
2021-10-22 |
Our paper Using linear algebra in decomposition of Farkas interpolants has been accepted to International Journal on Software Tools for Technology Transfer 2021 |
2021-06-24 |
Our paper Lattice-based SMT for program verification has been accepted MEMOCODE 2019 |
2021-06-24 |
Our paper Exploiting partial variable assignment in interpolation-based model checking has been accepted to Formal Methods in System Design 2019 |
2021-03-05 |
Our paper on Theory-Specific Proof Steps Witnessing Correctness of SMT Executions has been accepted to DAC 2021 |